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datasheet quad-frequency programmable vcxo idt8n4qv01 rev g idt8n4qv01gcd revision a march 11, 2014 1 ?2014 integrated device technology, inc. general description the idt8n4qv01 is a quad-frequency programmable vcxo with very flexible frequency and pull-range programming capabilities. the device uses idt?s fourth generation femtoclock? ng technology for an optimum of high clock frequency and low phase noise performance. the device accepts 2.5v or 3.3v supply and is packaged in a small, lead-free (rohs 6) 10-lead ceramic 5mm x 7mm x 1.55mm package. besides the 4 default power-up frequencies set by the fsel0 and fsel1 pins, the idt8n4qv01 can be programmed via the i 2 c interface to any output clock frequency between 15.476mhz to 866.67mhz and from 975mhz to 1,300mhz to a very high degree of precision with a frequency step size of 435.9hz n ( n is the pll output divider). since the fsel0 and fsel1 pins are mapped to 4 independent pll, p, m and n divider registers (p, mint, mfrac and n), reprogramming those registers to other frequencies under control of fsel0 and fsel1 is supported. the extended temperature range supports wireless infrastructure, tele- communication and networking end equipment requirements. features fourth generation femtoclock? ng technology programmable clock output frequency from 15.476mhz to 866.67mhz and from 975mhz to 1,300mhz four power-up default frequencies (see part number order codes), re-programmable by i 2 c i 2 c programming interface for the output clock frequency, apr and internal pll control registers frequency programming resolution is 435.9hz n absolute pull-range (apr) programmable from 4.5ppm to 754.5ppm one 2.5v or 3.3v lvds differential clock output two control inputs for the power-up default frequency lvcmos/lvttl compatible control inputs rms phase jitter @ 156.25mhz (12khz - 20mhz): 0.494ps (typical) rms phase jitter @ 156.25mhz (1khz - 40mhz): 0.594ps (typical) 2.5v or 3.3v supply voltage modes -40c to 85c ambient operating temperature lead-free (rohs 6) packaging idt8n4qv01 rev g data sheet 10-lead ceramic 5mm x 7mm x 1.55mm package body cd package top view 8v dd 7nq 6q fsel0 4 fsel1 5 10 sclk 9sdata vc 1 oe 2 gnd 3 pin assignment block diagram qnq osc 114.285 mhz mint, mfrac pfd & lpf femtoclock ? ng vco 1950-2600mhz n i 2 c control configuration register (rom) (frequency, apr, polarity) 25 7 vc fsel1fsel0 sclk sdata oe pulldown pulldown pullup pullup pullup a/d 7 p 2
idt8n4qv01gcd revision a march 11, 2014 2 ?2014 integrated device technology, inc. idt8n4qv01 rev g data sheet quad-frequency programmable-vcxo table 1. pin descriptions note: pullup and pulldown refer to internal input resistors. see table 2, pin characteristics, for typical values. table 2. pin characteristics number name type description 1 vc input vcxo control voltage. the control voltage versus frequency characteristics are set by the adc_gain[5:0] register bits. 2 oe input pullup output enable pin. see table 3b for function. lvcmos/lvttl interface levels. 3 gnd power power supply ground. 4, 5 fsel0, fsel1 input pulldown default frequency select pins. see table 3a for function and table 8 for the default frequency order codes. lvcmos/lvttl interface levels. 6, 7 q, nq output differential clock output. lvds interface levels. 8 v dd power power supply pin. 9 sdata input pullup i 2 c data input. lvcmos/lvttl interface levels. 10 sclk input pullup i 2 c clock input. lvcmos/lvttl interface levels. symbol parameter test conditions minimum typical maximum units c in input capacitance fsel[1:0], sdata, sclk 5.5 pf vc 10 pf r pullup input pullup resistor 50 k ? r pulldown input pulldown resistor 50 k ?
idt8n4qv01gcd revision a march 11, 2014 3 ?2014 integrated device technology, inc. idt8n4qv01 rev g data sheet quad-frequency programmable-vcxo function tables table 3a. default frequency selection note: the default frequency is the output frequency after power-up. one of four default frequencies is selected by fsel[1:0]. see programming section for details. table 3b. oe configuration note: oe is an asynchronous control. input operation fsel1 fsel0 0 (default) 0 (default) default frequency 0 0 1 default frequency 1 1 0 default frequency 2 1 1 default frequency 3 input output enable oe 0 outputs q, nq are in high-impedance state. 1 (default) outputs are enabled.
idt8n4qv01gcd revision a march 11, 2014 4 ?2014 integrated device technology, inc. idt8n4qv01 rev g data sheet quad-frequency programmable-vcxo block diagram with programming registers qnq osc 114.285 mhz pfd & lpf femtoclock? ng vco 1950-2600mhz n i 2 c control vc sclk sdata fsel[1:0] oe pulluppullup pulldown, pulldown pullup feedback divider m (25 bit) mint (7 bits) mfrac (18 bits) programming registers adc_gain adc_pol i 2 c: 6 bits 1 bit def: 6 bits 1 bit p0 mint0 mfrac0 n0 i 2 c: 2 bits 7 bits 18 bits 7 bits def: 2 bits 7 bits 18 bits 7 bits p1 mint1 mfrac1 n1 i 2 c: 2 bits 7 bits 18 bits 7 bits def: 2 bits 7 bits 18 bits 7 bits p2 mint2 mfrac2 n2 i 2 c: 2 bits 7 bits 18 bits 7 bits def: 2 bits 7 bits 18 bits 7 bits p3 mint3 mfrac3 n3 i 2 c: 2 bits 7 bits 18 bits 7 bits def: 2 bits 7 bits 18 bits 7 bits def: power-up default register setting for i 2 c registers 0001 10 11 34 34 34 34 34 7 34 7 30 30 30 30 18 output divider n a/d 7 adc_gainn, adc_pol, pn, mintn, mfracn and nn 7 7 41 p 2
idt8n4qv01gcd revision a march 11, 2014 5 ?2014 integrated device technology, inc. idt8n4qv01 rev g data sheet quad-frequency programmable-vcxo principles of operation the block diagram consists of the internal 3 rd overtone crystal and oscillator which provide the reference clock f xtal of either 114.285mhz or 100mhz. the pll includes the femtoclock ng vco along with the pre-divider ( p ), the feedback divider ( m ) and the post divider ( n ). the p , m , and n dividers determine the output frequency based on the f xtal reference and must be configured correctly for proper operation. the feedback divider is fractional supporting a huge number of output frequencies. the configuration of the feedback divider to integer-only values results in an improved output phase noise characteristics at the expense of the range of output frequencies. in addition, internal registers are used to hold up to four different factory pre-set p , m , and n configuration settings. these default pre-sets are stored in the i 2 c registers at power-up. each configuration is selected via the fsel[1:0] pins and can be read back using the sclk and sdata pins. the user may choose to operate the device at an output frequency diff erent than that set by the factory. after power-up, the user may write new p, n and m settings into one or more of the four configuration registers and then use the fsel[1:0] pins to select the newly programmed configuration. note that the i 2 c registers are volatile and a power supply cycle will reload the pre-set factory default conditions. if the user does choose to write a different p , m , and n configuration, it is recommended to write to a configuration which is not currently selected by fsel[1:0] and then change to that configuration after the i 2 c transaction has completed. changing the fsel[1:0] controls results in an immediate change of the output frequency to the selected register values. the p , m , and n frequency configurations support an output frequency range 15.476mhz to 866.67mhz and 975mhz to 1,300mhz. the devices use the fractional feedback divider with a delta-sigma modulator for noise shaping and robust frequency synthesis capability. the relatively high reference frequency minimizes phase noise generated by frequency multiplication and allows more efficient shaping of noise by the delta-sigma modulator. the output frequency is determined by the 2-bit pre-divider ( p ), the feedback divider (m) and the 7-bit post divider ( n ). the feedback divider ( m ) consists of both a 7-bit integer portion ( mint ) and an 18-bit fractional portion ( mfrac ) and provides the means for high-resolution frequency generation. the output frequency f out is calculated by: f out f xtal 1 pn ? ------------ - mint mfrac 0.5 + 2 18 ----------------------------------- + ?? = (1) the four configuration registers for the p, m (mint & mfrac) and n dividers which are named pn, mintn, mfracn and nn with n = 0 to 3. ?n? denominates one of the four possible configurations. as identified previously, the configurations of p , m (mint & mfrac) and n divider settings are stored the i 2 c register, and the configuration loaded at power-up is determined by the fsel[1:0] pins. input selects register fsel1 fsel0 0 (def.) 0 (def.) frequency 0 p0, mint0, mfrac0, n0 0 1 frequency 1 p1, mint1, mfrac1, n1 1 0 frequency 2 p2, mint2, mfrac2, n2 1 1 frequency 3 p3, mint3, mfrac3, n3 frequency configuration an order code is assigned to each frequency configuration programmed by the factory (default frequencies). for more information on the available default frequencies and order codes, please see the ordering information section in this document. for available order codes, see the femtoclock ng ceramic-package xo and vcxo ordering product information document. for more information and guidelines on programming of the device f or custom frequency configurations, the register description, the pull-range programming and the serial interface description, see the femtoclock ng ceramic 5x7 module programming guide. table 4. frequency selection
idt8n4qv01gcd revision a march 11, 2014 6 ?2014 integrated device technology, inc. idt8n4qv01 rev g data sheet quad-frequency programmable-vcxo absolute maximum ratings note: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only. functional operation of product at these conditions or any conditions beyond those listed in the dc characteristics or ac characteristics is not implied. exposure to absolute maximum rating conditions for extended periods may affect product reliability. supply voltage, v dd 3.63v inputs, v i -0.5v to v dd + 0.5v outputs, i o (sdata) outputs, i o (lvds) continuous current surge current 10ma10ma 15ma package thermal impedance, ? ja 49.4 ? c/w (0 mps) storage temperature, t stg -65 ? cto150 ? c dc electrical characteristics table 5a. power supply dc characteristics, v dd = 3.3v 5%, t a = -40c to 85c table 5b. power supply dc characteristics, v dd = 2.5v 5%, t a = -40c to 85c item rating symbol parameter test conditions minimum typical maximum units v dd power supply voltage 3.135 3.3 3.465 v i dd power supply current 160 ma symbol parameter test conditions minimum typical maximum units v dd power supply voltage 2.375 2.5 2.625 v i dd power supply current 155 ma
idt8n4qv01gcd revision a march 11, 2014 7 ?2014 integrated device technology, inc. idt8n4qv01 rev g data sheet quad-frequency programmable-vcxo table 5c. lvcmos/lvttl dc characteristic, v dd = 3.3v 5% or 2.5v 5%, t a = -40c to 85c table 5d. lvds dc characteristics, v dd = 3.3v 5% or 2.5v 5%, t a = -40c to 85c symbol parameter test conditions minimum typical maximum units v ih input high voltage sel [1:0], oe v cc =3.3v +5% 1.7 v cc +0.3 v sel [1:0], oe v cc =2.5v +5% 1.7 v cc +0.3 v v il input low voltage sel [1:0] v cc =3.3v +5% -0.3 0.5 v oe v cc =3.3v +5% -0.3 0.8 v sel [1:0] v cc =2.5v +5% -0.3 0.5 v oe v cc =2.5v +5% -0.3 0.8 v i ih input high current oe 10 a sdata,sclk v dd =v in = 3.465v or 2.625v 5 a fsel0,fsel1 v dd =v in = 3.465v or 2.625v 150 a i il input low current oe -500 a sdata,sclk v dd = 3.465v or 2.625v, v in =0v -150 a fsel0,fsel1 v dd = 3.465v or 2.625v, v in =0v -5 a symbol parameter test conditions minimum typical maximum units v od differential output voltage 247 350 454 mv ? v od v od magnitude change 50 mv v os offset voltage 1.0 1.20 1.375 v ? v os v os magnitude change 50 mv
idt8n4qv01gcd revision a march 11, 2014 8 ?2014 integrated device technology, inc. idt8n4qv01 rev g data sheet quad-frequency programmable-vcxo ac electrical characteristics table 6a. vcxo control voltage input (v c ) characterisitics, v dd = 3.3v 5% or 2.5v 5%, t a = -40c to 85c note: electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. the device will meet specifications after thermal equilibrium has been reached under these conditions. note 1: v c =0vtov dd . note 2: nominal oscillator gain: pull range divided by the control voltage tuning range of 3.3v. e.g. for adc_gain[6:0] = 00.0001 the pull range is 12.5ppm, resulting in an oscillator gain of 2 * 12.5ppm 3.3v = 7.57ppm/v. note 3: for best phase noise performance, use the lowest k v that meets the requirements of the application. note 4: bsl = best straight line fit: variation of the output frequency vs. control voltage v c , in percent. v c ranges from 10% to 90% v dd . note 5: incremental slope is defined as the linearity in percent of the raw data (not relative to bsl) from 10% to 90% v dd . symbol parameter test conditions minimum typical maximum units k v oscillator gain, note 1, 2, 3 v dd = 3.3v adc_gain[5:0] = 000001 7.57 ppm/v adc_gain[5:0] = 000010 15.15 ppm/v adc_gain[5:0] = xxxxxx 212.5 v dd adc_gain ppm/v adc_gain[5:0] = 111110 469.69 ppm/v adc_gain[5:0] = 111111 477.27 ppm/v oscillator gain, note 1, 2, 3 v dd = 2.5v adc_gain[5:0] = 000001 10 ppm/v adc_gain[5:0] = 000010 20 ppm/v adc_gain[5:0] = xxxxxx 212.5 v dd adc_gain ppm/v adc_gain[5:0] = 111110 620 ppm/v adc_gain[5:0] = 111111 630 ppm/v l vc control voltage linearity bsl variation; note 4 -5 1 +5 % incremental; note 5 -10 5 +10 % bw modulation bandwidth 100 khz z vc vc input impedance 500 k ? vc nom nominal control voltage v dd 2 v v c control voltage tuning range; note 4 0v dd v
idt8n4qv01gcd revision a march 11, 2014 9 ?2014 integrated device technology, inc. idt8n4qv01 rev g data sheet quad-frequency programmable-vcxo table 6b. ac characteristics, v dd = 3.3v 5% or 2.5v 5%, t a = -40c to 85c note: electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. the device will meet specifications after thermal equilibrium has been reached under these conditions. all ac parameters are characterized with p=1 and pull range 250 ppm. note: xtal parameters (initial accuracy, temperature stability, aging and total stability) are guaranteed by manufacturing. note 1: this parameter is defined in accordance with jedec standard 65. note 2: please refer to the phase noise plots. notes continued on next page. symbol parameter test conditions minimum typical maximum units f out output frequency q, nq output divider, n = 3 to126 15.476 866.67 mhz output divider, n = 2 975 1,300 mhz f vco vco frequency 1980 2600 mhz f i initial accuracy measured at 25c 10 ppm f s temperature stability option cod e=aorb 100 ppm option cod e=eorf 50 ppm option cod e=korl 20 ppm f a aging frequency drift over 10 year life 3 ppm frequency drift over 15 year life 5 ppm f t total stability option code a or b (10 year life) 113 ppm option code e or f (10 year life) 63 ppm option code k or l (10 year life) 33 ppm t jit(cc) cycle-to-cycle jitter; note 1 20 ps t jit(per) period jitter; note 1 2.85 4 ps t jit(?) rms phase jitter (random) fractional pll feedback and f xtal =114.285mhz (0xxx order codes) 17mhz ?? f out ?? 1300mhz, note 2,3,4 0.475 0.990 ps f out ?? 156.25mhz, note 2, 3, 4 0.494 0.757 ps f out ?? 156.25mhz, note 2, 3, 5 0.594 ps ? n (100) single-side band phase noise, 100 hz from carrier 156.25mhz -73.8 dbc/hz ? n (1k) single-side band phase noise, 1khz from carrier 156.25mhz -99.8 dbc/hz ? n (10k) single-side band phase noise, 10khz from carrier 156.25mhz -126.1 dbc/hz ? n (100k) single-side band phase noise, 100khz from carrier 156.25mhz -129.3 dbc/hz ? n (1m) single-side band phase noise, 1mhz from carrier 156.25mhz -140.3 dbc/hz ? n (10m) single-side band phase noise, 10mhz from carrier 156.25mhz -144.3 dbc/hz psnr power supply noise rejection 50mv sinusoidal noise 1khz - 50mhz -54 db t r /t f output rise/fall time 20% to 80% 100 425 ps odc output duty cycle 45 55 % t osc oscillator start-up time 20 ms t set output frequency settling time after fsel0 and fsel1 values are changed 470 s
idt8n4qv01gcd revision a march 11, 2014 10 ?2014 integrated device technology, inc. idt8n4qv01 rev g data sheet quad-frequency programmable-vcxo note 3: please see the femtoclock ng ceramic 5x7 modules programming guide for more information on finding the optimum configuration for phase noise. note 4: integration range: 12khz-20mhz. note 5: integration range: 1khz-40mhz. typical phase noise at 156.25mhz (12khz - 20mhz) noise power dbc hz offset frequency (hz)
idt8n4qv01gcd revision a march 11, 2014 11 ?2014 integrated device technology, inc. idt8n4qv01 rev g data sheet quad-frequency programmable-vcxo parameter measurement information 3.3v lvds output load ac test circuit rms phase jitter output duty cycle/pulse width/period 2.5v lvds output load ac test circuit period jitter cycle-to-cycle jitter scope q nq 3.3v5% power suppl + float gnd v dd t pw t period t pw t period odc = x 100% nq q scope q nq 2.5v5% power suppl + float gnd v dd v oh v ref v ol mean period (first edge after trigger) reference point (trigger edge) 1 contains 68.26% of all measurements 2 contains 95.4% of all measurements 3 contains 99.73% of all measurements 4 contains 99.99366% of all measurements 6 contains (100-1.973x10 -7 )% of all measurements histogram nq q ? ? ? ? t cycle n t cycle n+1 t jit(cc) = t cycle n t cycle n+1 1000 cycles
idt8n4qv01gcd revision a march 11, 2014 12 ?2014 integrated device technology, inc. idt8n4qv01 rev g data sheet quad-frequency programmable-vcxo parameter measurement information (continued) output rise/fall time differential output voltage setup start-up offset voltage setup 20% 80% 80% 20% t r t f v od nq q t startup not to scale v dd min v dd output correct frequency ? ?
idt8n4qv01gcd revision a march 11, 2014 13 ?2014 integrated device technology, inc. idt8n4qv01 rev g data sheet quad-frequency programmable-vcxo applications information recommendations for unused input pins inputs: lvcmos select pins all control pins have internal pulldowns; additional resistance is not required but can be added for additional protection. a 1k ? resistor can be used. lvds driver termination for a general lvds interface, the recommended value for the termination impedance (z t ) is between 90 ? and 132 ? . the actual value should be selected to match the differential impedance (z 0 )of your transmission line. a typical point-to-point lvds design uses a 100 ? parallel resistor at the receiver and a 100 ? differential transmission-line environment. in order to avoid any transmission-line reflection issues, the components should be surface mounted and must be placed as close to the receiver as possible. idt offers a full line of lvds compliant devices with two types of output structures: current source and voltage source. the standard termination schematic as shown in figure 1a can be used with either type of output structure. figure 1b , which can also be used with both output types, is an optional termination with center tap capacitance to help filter common mode noise. the capacitor value should be approximately 50pf. if using a non-standard termination, it is recommended to contact idt and confirm if the output structure is current source or voltage source type. in addition, since these outputs are lvds compatible, the input receiver?s amplitude and common-mode input range should be verified for compatibility with the output. lvds driver lvds driver lvds receiver lvds receiver z t c z o ? z t z o ? z t z t 2 z t 2 figure 1a. standard termination figure 1b. optional termination lvds termination
idt8n4qv01gcd revision a march 11, 2014 14 ?2014 integrated device technology, inc. idt8n4qv01 rev g data sheet quad-frequency programmable-vcxo power considerations this section provides information on power dissipation and junction temperature for the idt8n4qv01. equations and example calculations are also provided. 1. power dissipation. the total power dissipation for the idt8n4qv01 is the sum of the core power plus the power dissipated in the load(s). the following is the power dissipation for v dd = 3.3v + 5% = 3.465v, which gives worst case results. ? power (core) max =v dd_max *i dd_max = 3.465v * 160ma = 554.4mw 2. junction temperature. junction temperature, tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. the maximum recommended junction temperature is 125c. limiting the internal transistor junction temperature, tj, to 125c ensures that the bond wire and bond pad temperature remains below 125c. the equation for tj is as follows: tj = ? ja * pd_total + t a tj = junction temperature ? ja = junction-to-ambient thermal resistance pd_total = total device power dissipation (example calculation is in section 1 above) t a = ambient temperature in order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance ? ja must be used. assuming no air flow and a multi-layer board, the appropriate value is 49.4c/w per table 7 below. therefore, tj for an ambient temperature of 85c with all outputs switching is: 85c + 0.554w * 49.4c/w = 112.4c. this is below the limit of 125c. this calculation is only an example. tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of board (multi-layer). table 7. thermal resistance ? ja for 10 lead ceramic 5mm x 7mm package, forced convection ? ja by velocity meters per second 0 1 2.5 multi-layer pcb, jedec standard test boards 49.4c/w 44.2c/w 41c/w
idt8n4qv01gcd revision a march 11, 2014 15 ?2014 integrated device technology, inc. idt8n4qv01 rev g data sheet quad-frequency programmable-vcxo reliability information table 8. ? ja vs. air flow table for a 10-lead ceramic 5mm x 7mm package transistor count the transistor count for idt8n4qv01 is: 47,372 ? ja vs. air flow meters per second 0 1 2.5 multi-layer pcb, jedec standard test boards 49.4c/w 44.2c/w 41c/w
idt8n4qv01gcd revision a march 11, 2014 16 ?2014 integrated device technology, inc. idt8n4qv01 rev g data sheet quad-frequency programmable-vcxo package outline and package dimensions
idt8n4qv01gcd revision a march 11, 2014 17 ?2014 integrated device technology, inc. idt8n4qv01 rev g data sheet quad-frequency programmable-vcxo ordering information for femtoclock ng ceramic-package xo and vcxo products the programmable vcxo and xo devices support a variety of devices options such as the output type, number of default frequen- cies, internal crystal frequency, power supply voltage, ambient temperature range and the frequency accuracy. the device options, default frequencies and default vcxo pull range must be specified at the time of order and are programmed by idt before the shipment. the table below specifies the available order codes, including the device options and default frequency configurations. example part number: the order code 8n3qv01fg-0001cdi specifies a programmable, quad default-frequency vcxo with a voltage supply of 2.5v, a lvpecl output, a ? 50 ppm crystal frequency accuracy, contains a 114.285mhz internal crystal as frequency source, industrial temperature range, a lead-free (6/6 rohs) 10-lead ceramic 5mm x 7mm x 1.55mm package and is factory-programmed to the default frequencies of 100, 122.88, 125 and 156.25mhz and to the vcxo pull range of min. ? 100 ppm. other default frequencies and order codes are available from idt on request. for more information on available default frequencies, see the femtoclock ng ceramic-package xo and vcxo ordering product information document. shipping package 8 : tape & reel (no letter): tray ambient temperature range ? i ?: industrial: (t a = -40c to 85c) (no letter) : (t a = 0c to 70c) package code cd : lead-free, 6/10-lead ceramic 5mm x 7mm x 1.55mm die revision g (opt. 207) option code (supply voltage and frequency-stability) a :v cc = 3.3v5%, 100ppm b :v cc = 2.5v5%, 100ppm e :v cc = 3.3v5%, 50ppm f :v cc = 2.5v5%, 50ppm k :v cc = 3.3v5%, 20ppm l :v cc = 2.5v5%, 20ppm default-frequency and vcxo pull range see document femtoclock ng ceramic-package xo and vcxo ordering product information. last digit = l : configuration pre-programmed and not changeable dddd f xtal (mhz) pll feedback use for 0000 to 0999 114.285 fractional vcxo, xo 1000 to 1999 100.000 integer xo 2000 to 2999 fractional xo femtoclock ng i/o identifier 0 : lvcmos 3 : lvpecl 4 : lvds number of default frequencies s : 1: single d : 2: dual q : 4: quad part number function #pins oe fct. at pin 001 xo 10 oe@2 003 xo 10 oe@1 v01 vcxo 10 oe@2 v03 vcxo 10 oe@1 v75 vcxo 6 oe@2 v76 vcxo 6 noe@2 v85 vcxo 6 ? 085 xo 6 oe@1 270 xo 6 oe@1 271 xo 6 oe@2 272 xo 6 noe@2 273 xo 6 noe@1 8n x x xxx x x - dddd xx x x part/order number
idt8n4qv01gcd revision a march 11, 2014 18 ?2014 integrated device technology, inc. idt8n4qv01 rev g data sheet quad-frequency programmable-vcxo table 9. device marking marking industrial temperature range (t a = -40c to 85c) commercial temperature range (t a = 0c to 70c) idt8n4 x v01 y g- dddd cdi idt8n4 x v01 y g- dddd cd x = number of default frequencies, y = option code, dddd =default-frequency and vcxo pull range
idt8n4qv01gcd revision a march 11, 2014 19 ?2014 integrated device technology, inc. idt8n4qv01 rev g data sheet quad-frequency programmable-vcxo revision history sheet rev table page description of change date a t9 18 table 9 device marking, corrected marking. 3/6/12 a t1 t6a 28 deleted ?(see table 3c)? from the first table row, description column. note 2; deleted ?from table 3c?. 3/13/14
disclaimer integrated device technology, inc. (idt) and its subsidiaries reserve the right to modify the products and/or specif ications described herein at any time and at idts sole discretion. all information in this document, including descriptions of product features and performance, is subject to change without notice. performance specifications and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when installed in customer products. the information contained herein is provided without representation or warranty of any kind, whether express or implied, includi ng, but not limited to, the suitability of idts products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. this document is presented only as a guide and does not convey any license under intellectual property rights of idt or any third parties. idts products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an idt product can be reasonably expected to signifi- cantly affect the health or safety of users. anyone using an idt product in such a manner does so at their own risk, absent an express, written agreement by idt. integrated device technology, idt and the idt logo are registered trademarks of idt. other trademarks and service marks used herein, including protected names, logos and designs, are the property of i dt or their respective third party owners. copyright 2014. all rights reserved. 6024 silver creek valley road san jose, california 95138 sales800-345-7015 (inside usa) +408-284-8200 (outside usa) fax: 408-284-2775 www.idt.com/go/contactidt technical support sales netcom@idt.com+480-763-2056 weve got your timing solution idt8n4qv01 rev g data sheet quad-frequency programmable-vcxo

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